1. Field of the Invention
The invention relates to a level shifter, and more particularly, to a level shifter for shifting the voltage level of a logic signal from a high operating voltage to a low operating voltage.
2. Description of the Prior Art
In an integrated circuit, because of the concerns of power and integration, the operating voltage of the integrated circuit is usually smaller than the operating voltage of an external system. Take an integrated circuit using 1.2V as the operating voltage as an example, 1.2V and 0V are used to represent logic value 1 and 0 respectively. But an external circuit usually uses higher voltage as the operating voltage than the integrated circuit. For example, the operating voltage of circuit elements on a motherboard is normally 5V or 3.3V, that is, 5V or 3.3V is used to represent logic value 1, while 0V is used to represent logic value 0. Accordingly, in an integrated circuit, a device must be set for shifting the level of a logic signal switching between 5V (or 3.3V) and 0V into a logic signal switching between 1.2V and 0V, which is termed “high-to-low level shifter” hereinafter.
In an integrated circuit, a component operating at 5V/3.3V is conventionally called high-voltage element; a component operating at 1.2V is conventionally called low-voltage element. Take a metal-oxide-semiconductor transistor (MOS transistor) as an example, being a high-voltage element or a low-voltage element is determined by the thickness of the oxide-layer of the MOS transistor. Generally speaking, a high-voltage MOS transistor has thicker oxide-layer than a low-voltage MOS transistor. Consequently, the threshold voltage of the high-voltage MOS transistor is larger than the threshold voltage of the low-voltage MOS transistor. Normally a high-voltage MOS transistor has a nominal threshold voltage of 0.9V.
Please refer to FIG. 1, a circuit diagram of a conventional high-to-low level shifter is illustrated. In FIG. 1 a high-to-low level shifter 100 is set inside an integrated circuit 150, and is coupled to an external circuit 180. The operating voltages of the external circuit 180 are: VDDH=3.3V, VSSH=0V, and the operating voltages of the integrated circuit 150 are: VDDL=1.2V, VSSL=0V. The high-to-low level shifter 100 includes: a high-voltage PMOS transistor 140 and a high-voltage NMOS transistor 160. Because the level shifter 100 receives the logic signal from the external circuit 180, the elements of the level shifter 100 are preferably high-voltage elements. When an external signal SH1 is at logic 1, its potential equals VDDH, the high-voltage NMOS transistor 160 will be turned on, and as a result the potential of an internal signal SL1 will be pulled down to VSSL. On the contrary, when the external signal SH1 is at logic 0, its potential equals VSSH, the high-voltage PMOS transistor 140 will be turned on, and as a result the potential of the internal signal SL1 will be pulled up to VDDL.
Please refer to FIG. 2, an example of logic signals in FIG. 1 is illustrated. From FIG. 2 it can be seen that under circumstances described above, logic signals can pass through the high-to-low level shifter 100 correctly.
But with advanced technology on integrated circuit processes, the operating voltage of the integrated circuit becomes smaller and smaller. For example, an integrated circuit produced through advanced technology can have operating voltage lower than 1.2, such as 0.9V or even lower. Under such circumstances the high-to-low level shifter 100 of FIG. 1 will probably pass logic signals wrongly.
Take VDDL=1V as an example (assume other parameters are unchanged). When the potential of the external signal SH1 equals VDDH, the potential of the internal signal SL1 will be pulled down to VSSL by the high-voltage NMOS transistor 160. However, when the potential of the external signal SH1 equals VSSH, even though the channel between the drain and the source of the high-voltage PMOS transistor 140 is turned on, the equivalent resistance of the channel is not small enough to be ignored, so it takes much more time for the internal signal SL1 to raise toward VDDL, and the switching time for the integrated circuit 150 is then increased. Under an extreme situation, while the operating frequency of the external signal SH1 is raised, each time when the potential of the external signal SH1 equals VSSL, the time period may not be enough for the potential of the internal signal SL1 to rise to VDDL. Under such circumstances the logic signal outputted (SL1) by the level shifter 100 will be incorrect as it is shown in FIG. 3.
When VDDL equals 0.9V, or even smaller than 0.9V (assume that other parameters are unchanged), because the threshold voltage of high-voltage elements is 0.9V, when the potential of the external signal equals VSSH, the channel of the high-voltage PMOS transistor 140 will not be turned on, and accordingly the logic signals outputted (SL1) by the level shifter 100 will be incorrect as it is shown in FIG. 4.
As depicted above, one difficulty the high-to-low level shifter in FIG. 1 faces is that logic signal probably can not pass through the high-to-low level shifter correctly when the operating voltage of the integrated circuit becomes smaller and smaller.